copper contamination semiconductor

By:

Date: 12/12/2022

Therefore, a barrier film is required to ensure the increased profitability that should accompany the introduction of the Cu interconnect. Theoretically, however, during chemical mechanical planarization (CMP), the exclusion zone would be free of Cu, but serious concerns remain for cross-contamination from the remaining Cu film on the beveled edge. In Cu CMP process, the excess Cu film and metal barrier layer must be removed to fabricate Cu metallization. H. Oppolzer, W. Eckers, and H. Schaber, J. Phys. Tata has already announced a partnership with Tokyo-based Renesas Electronics in June this year, noted the report, which is based around semiconductor design and development. The minimum feature size has advanced from 10m down to 10nm, the cost per transistor has decreased by seven orders of magnitude, and the maximum number of transistors per chip has increased by at least 10 orders of magnitude [1]. Due to the presence of the TaN layer, the chamfering at the top corner of vias and trenches and the re-sputtered Cu atoms and contaminations into the dielectric can be effectively reduced during Ar sputtering clean process. Sputtering deposition is the preferred method to deposit the Cu seed layer because it can produce high-purity films. Maximum required current density at 105C for M-1 Cu lines with technology nodes [40]. Chem. The EM-induced void will form inside the via (early failure) and in the wire (late failure). copper and consumed-silicon atoms from the silicon substrate. The formation of Cu compound (Cu3N) at the interface for providing a better interface is a possible mechanism. We determined that a key point to successful use of SPCE is the presence of a barrier film. The emerging use of copper (Cu) is driving the need for control of any potential Cu cross contamination that could affect yields and fab productivity. The industry appears to have settled on electroplate deposition for blanket Cu plating of wafers. J. Electrochem. The presence of metallic contaminants affects the performances of a device in drastic ways. In the past two decades, better performance of ICs was achieved by using Cu conductor in place of Al conductor. Copper exhibits the highest diffusivity and solubility of all transition metals and can be diffused easily to the bulk of the wafer during thermal processing steps. Relative diffusivity of copper compared to other metals, at 700C, is shown in Figure 1. CRC Handbook of Metal Etchants, eds. Wafer and cassette carriers should be clearly identified and be cleaned to prevent copper material build-up. Since the time-dependent dielectric breakdown is used to assess the dielectric reliability, its performance is strongly dependent on the property of a dielectric. This fact amazed the production people, but anyone who has worked on semiconductor processes knows that you can never just look at the usual suspects. During CMP process, the wafers are placed face-down on a rotating pad on which the slurry is dispensed, resulting in the removal of the film by chemical reaction and mechanical force. This failure mode of stress-induced voids can be eliminated with good metal barrier layer coverage on the bottom and sidewalls of trenches and vias and void-free Cu-filling process. This will enable fabs to determine, during a pilot-line phase, where, when, and how often cleans should take place and what contamination level is acceptable. Furthermore, Mn is the promising candidate for providing some advantages. The primary objective of this strategy is the development of a plan that will ensure the safe introduction and operation of copper in the cleanroom or fabrication facility. We used vapor phase dissolution inductively coupled plasma mass spectrometry (VPD-ICP-MS or VPD) to measure the beveled edge. Chapter 5X (3) - Free download as PDF File (.pdf), Text File (.txt) or read online for free. (A) Dielectrics (SiN/SiCN, SiCOH, SiO2) deposition; (B1) Via-1 lithography and RIE; (B2) M-2 trench lithography and RIE; (C1) ARC plug; (C2) Via-1 lithography; (D1) M-2 trench lithography and RIE and etching stop layer opening; (D2) Via-1 RIE; (E) metal barrier and Cu seed deposition; (F) electroplating Cu deposition; and (G) Cu CMP and dielectric barrier deposition. As the dimensions of Cu interconnects shrink, these two processes are becoming more challenging. P. Lysaght et al., A Novel Wafer Backside Spin-Process Contamination Elimination for Advanced Copper Device Applications, ECS, October 1999. Separation of work areas (copper and non-copper bay) can range from total isolation at one end of the spectrum to small island-isolation at the other end, providing the least amount of risk to maximum amount of contamination risk respectively. Stress-induced void in Cu lines are mostly observed under vias [116]. There are four primary routes for copper cross contamination to FEOL applications: * Direct physical contact of copper wafers to FEOL applications by error. The open pore in the porous low-k film allows water and other contaminations to diffuse into the dielectric. Consequently, ECP process can provide a void-free filling process for via and trench dual damascene structure under an adequate combination of suppressor and accelerator additives. Gate oxide areas with low breakdown fields of about 2-3 MV/cm were located in a pinhole detector and correlate very well with the contaminated areas revealed by Secco defect etching. Additionally, Cu metallization also influences the TDDB performance. The so-called chain effect from a single contaminated tool to many other tools can be prevented only by proper development of an appropriate segregation strategy. 1 and Fig. One such yield related challenge is to control the copper contamination of the front-end-of-line (FEOL) processes. This chapter is distributed under the terms of the Creative Commons Attribution 3.0 License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Still to be resolved is the removal of Cu processing's tantalum tantalum-nitride film from the exclusion zone. Conversion of non-copper parts to copper parts and vice-versa. Careful determination of feasibility is required for conversion of non-copper parts to copper parts. * Contamination of wafers from partially contaminated wafers in bulk phase. Selecting this option will search the current publication in context. The wafer backside can be hermetically sealed during Cu deposition, but this leaves the beveled edge and front-side exclusion zone exposed to Cu contamination. Our team is growing all the time, so were always on the lookout for smart people who want to help us reshape the world of scientific publishing. In order to fabricate Cu dual damascene interconnects, various process flows were developed. Identification of contamination sources and an understanding of the risk of copper contamination is key to the successful implementation of procedures to control and prevent such contamination to FEOL and non-copper BEOL processes. However, the issues of Cu diffusion into the dielectric, metal barrier layer coverage on the bottom and sidewalls of trenches and vias and Cu plating gap filling are important. Traditionally, low concentrations of metals in plating solutions can be monitored using highly sensitive polarography methods or spectral methods such as AAS or ICP [1]. 3. Energy-dispersive-spectrometry (EDS) data, however, indicate that these rings are not 100% effective in preventing Cu deposition in the exclusion zone (Fig. However, control of this process can make a significant improvement on reliability for Cu interconnects if it is controlled precisely. Instead, E1/2-model [146, 166] is the most appropriate model. Moreover, Mn has high affinity for oxygen, resulting in the formation of MnOx layer with the dielectric film by annealing. Thus, no further EM lifetime improvement is observed at the operation frequencies above this point [88]. Moreover, low downforce during the over-polish step in Cu CMP process is required to minimize this effect from the perspective of the process [69]. One possible scenario is the adoption of a stand-alone system. The metal deposition in the dual damascene structure consists of three steps: Cu barrier layer, Cu seed layer, and bulk Cu layer. 2. Nitric acid (HNO3) is an oxyacid and as such is a strong electrolyte and a powerful oxidizing agent that is considered 100% ionized in aqueous solution (H2O). By using our websites, you agree to placement of these cookies and to our. The barrier film is key to yield enhancement and overall cost reduction. Moreover, a barrier-first process was provided to minimize the detrimental effects caused by Ar sputtering clean [59]. The most common reduction products of nitric acid are NO2 (N = 4), NO (N = 2), and NH4+ (N = -3). Means for control and prevention of copper contamination are outlined above. A number of surface (front and back) contamination and bulk recombination lifetime measurement tools or techniques can be used to monitor copper contamination on test wafers from a specific wafer processing tool. To construct multiple metal levels, these steps are repeated for each metal level. Control of etchant viscosity, simultaneous radial and tangential etchant flows, and Bernoulli gas flow enables etching of Cu contamination from a wafer backside, and a wraparound effect that removes thin-film contamination from the beveled edge and front-side exclusion zone (0.5-5.0mm). Therefore, a multilayer film of Ti/TiN/Ti is used as a Cu diffusion barrier layer; TiN can prevent excessive reaction between Ti and Cu, which can increase the resistivity of the wire. What about wafer rework and equipment flexibility? Crystec Technology Trading GmbH Copper anneal in semiconductor manufacturing. In the Cu interconnects, there are three main reliability items: electromigration (EM), stress-induced voiding (SIV), and time-dependent dielectric breakdown (TDDB) [18]. The first EM-related failure of Al-interconnect based circuit was observed in 1966 [73]. L. E. Davis, N. C. MacDonald, P. W. Palmberg, G. E. Riach, and R. E. Weber. How? The diffusion barrier layer on the top of Cu wires is typically a dielectric barrier film. But after the second step in the process, the silicon etch, Cu is generally below detection limits. *Address all correspondence to: yjcheng@ncnu.edu.tw. However, there remain many challenges to solve for etching of Cu including etching chemistry, hardmask, and hardware. Resistivity of metal line and thickness of Cu barrier layer with technology nodes [40]. Any Cu contamination is driven into barrier films or silicon on the beveled edge and backside during Cu annealing. Bulk measurement techniques include surface photo voltage (SPV), microwave photoconductive decay (u-PCD) or deep level transient spectroscopy (DLTS). 1). Thus, a layer of Cu dual damascene structure (via and trench) is finished. Soc., Vol. Surface contamination from these tools can be greatly reduced or eliminated by wiping down with alcohol. Therefore, the drawback of using chemical plasma cleaning to remove Cu oxides is the plasma-induced damage on the dielectric (e.g. The reaction in Eqn. - Conception and design of experimental setups and laser machine tools (kinematics and control). Semiconductor Advanced Electronics Specialty Industrial Industrial Technologies Life & Health Sciences Research & Defense Support Global Service Field Service Extended Warranty Program Repair, Calibration & Refurbishment RMA Request Form Health & Safety Forms Contact Global Service Technical Support Product Technical Support Training Programs Reproduced with permission from Ref. VPD results showed 8.3 x 1010 Cu atoms/cm2. A well developed peak at about 8 keV is possibly a copper K~, and copper K~ is probably . 1 Ohmi,T. NMOS and PMOS transistors of various (W/L) ratios, down to 0.24m channel length, have been used to investigate the effects of copper diffusion (from the backside) on their electrical parameters. Nanoparticle-Catalyzed Growth of Semiconductor Nanowires. So, a TaN/Ru or Ti/Ru bilayer is used for Cu diffusion barrier [54, 55, 56]. During the fabrication of Cu dual damascene structure, there are two stages in which Cu film could be exposed to air. I. It is postulated that the accelerated electrons, injected from the cathode, transport inside low-k dielectric by means of Schottky-Emission or Poole-Frenkel conduction. handbook-for-cleaning-for-semiconductor-manufacturing-fundamentals-and-applications 1/10 Downloaded from hosting1.mat.uc.cl on . The indiffusion of copper and/or oxidation were performed in a rapid thermal annealing system. Considerable effort has been made in recent years to evaluate the detrimental effect of metals including copper, on the integrity of thin gate oxide in FEOL application. The method includes the steps of providing the first layer having a partially . Diffusion process caused by EM can be divided into bulk diffusion, grain boundary diffusion, surface diffusion, and interface diffusion. This condition is further exacerbated by current trends that minimize the exclusion zone to 3mm and even 2mm (as specified by different semiconductor manufacturers), effectively putting the deposited Cu blanket onto the beveled edge. In order to slow down the increase of RC delay, the possible solution is to change the materials used in the BEOL interconnects. According to the present invention, a semiconductor wafer (102) is transferred (108) from a semiconductor manufacturing component (104), which may have exposed the wafer to copper contamination, to a measurement system (106). They all have their own idea of where and how they want Cu systems integrated and to what extent they will sacrifice flexibility. Wafers sat in these tubes while the oven heated and diffusion gases flowed over the wafers. In order to obtain the coefficients of the most probable chemical reaction for copper plating, the ratio between the numbers of consumed silicon atoms (n Si) Determination of baselines for process tolerance of copper contamination is key to the development of effective preventive measures for the prevention of copper contamination. The 1997 National Technology Roadmap for Semiconductors established target levels for critical metals, including nickel, Cu, and sodium, at <=2.5 x 1010 atoms/cm2 for the 250nm technology node and <=1.3 x 1010 atoms/cm2 for the 180nm node. Copper is used at back-end-of-line (BEOL) processes for interconnect metallization and can cause cross-contamination to FEOL applications. By clicking Accept All, you consent to the use of ALL the cookies. Nickel, electroplating, copper, contamination. Gowning requirements for working in cleanroom chase areas are particularly important since particle generation in certain chases in proximity to copper tools can increase the risk of copper contamination. If stress-induced void is originated from thermal expansion mismatch during the dielectric capping layer deposition, a stress-free temperature can be obtained. The latter method is widely used in the semiconductor industry. Processes and procedures must be developed to control such cross-contamination while also controlling cycle time and cost. These steps will increase the effective dielectric constant, raising the capacitance. Astatine is a chemical element with the symbol At and atomic number 85. However, as the technology node of ICs is continuously advancing, the lateral electric field across the BEOL dielectric significantly increases due to the reduction of interconnect dimension. The most effective method to maximize Cu grain size is by the use of an annealing process. Functional cookies help to perform certain functionalities like sharing the content of the website on social media platforms, collect feedbacks, and other third-party features. First, the modulus of the low-k dielectrics is lower than that of SiO2 film and decreases with the reduction of the dielectric constant. Deposition and dry etching contribute to contamination of the wafer backside and at the edge. (1) and (2), respectively. part of the Developments in Surface Contamination and Cleaning series provide a state-of-the-art guide In contrast to the large Expand 10 PDF Save Alert Finally, short conclusion and future trend for conductors used in the BEOL interconnects are provided in Section 6. Among all metals in the world, three kinds of metal have lower resistivity than Al with a resistivity of 2.65 -cm: Gold (Au; 2.214 cm), copper (Cu; 1.678 cm), and silver (Ag: 1.587 cm). Overall, Cu contamination has been a challenge in the field of Si semiconductor devices. The team ran many experiments and tried several approaches to determine the source of the contamination. In this theory, Cu could act as a precursor for an ultimate dielectric breakdown. A sample of the pure element has never been assembled, because any macroscopic . With the reduction of interconnect dimensions in the advanced technology nodes, this problem is becoming thrilling. Additional investigations have indicated that a high density of defect sites in the as-deposited dielectric (especially for low-k materials) [151], damage or contamination of the dielectric from processes such as plasma and CMP processes [152, 153, 154], and patterning problems such as line edge roughness or via misalignment [155, 156] resulted in the low breakdown strength of BEOL dielectrics. Failure to remove Cu from the exclusion zone may not be detrimental to the device, since diffusion through tantalum nitride is minimal below 400C [4]. However, its Cu barrier efficiency and adhesion ability with Cu film are poorer than those of a metal barrier layer. (A) TiN, ARC, and resist deposition; (B) M-2 metal hardmask RIE; (C) M-2 trench lithography; (D) Via-1 lithography; (E) Via-1 RIE; (F) M-2 oxide hardmask RIE; (G) M-2/Via-1 RIE and M-1 capping layer RIE; and (H) M-2/Via-1 Cu metallization. In addition to the need of lower resistivity, the other requirement for Cu film is to fill the high aspect ratio vias and trenches without voids in the dual damascene structure. Each of the support functions should be carefully evaluated for segregation to minimize any risk to cleanroom operation. Like EM, voids will form in the metal line for stress-induced voiding. Browse the most current issue of R&D World and back issues in an easy to use high quality format. Typically, there are three main steps in Cu CMP process [64]. This also includes contact with copper contaminated tools or materials used in processing copper wafers coming in contact with wafers or materials used in FEOL applications. We have studied the Cu contamination effect on 4.2 nm thick Al 2 O 3 metal-oxide semiconductor (MOS) capacitors with an equivalent-oxide thickness (EOT) of 1.9 nm. There's just one problem - the seam is within the site of Southern Copper Corp's planned $2.6 billion Los Chancas mine. Such contamination can be removed after the anneal, but additional sacrificial film is consumed during what amounts to an elongated cleaning process sequence that depends on the sacrificial backside film used, or lack thereof, and depth of Cu diffusion. However, as the technology node is advanced to 0.25m, the back-end-of-line (BEOL) interconnect of ICs becomes the bottleneck in the improvement of IC performance [2]. CMP processes can only remove copper from the face of the wafer, leaving any film or contamination on the beveled edge free to migrate during subsequent operations. Generally, technology node advances every 2 years with the shrinkage of the feature size by 0.7 times. Common exhaust systems, if they exist, between copper and non-copper tools must be evaluated and properly balanced to prevent cross-contamination. To achieve adequate conformity in high aspect ratio via and trench in the dual damascene structure for advanced technology nodes, ionized PVD [34] or atomic layer deposition (ALD) [35] technologies have been developed for Cu seed layer deposition with demonstrated good step-coverage. The dielectric is damaged by plasma irradiation. Thus, more integration challenges are raised, as described below: As the dimensions of Cu interconnects are reduced, the resistivity increases dramatically due to grain boundary scattering, surface scattering, and an increasing fraction of refractory metal liner in the trench (Figure3) [38, 39]. Other uncategorized cookies are those that are being analyzed and have not been classified into a category as yet. A low cycle fatigue life of 10,000 cycles or more at 823 K (550 deg.C) at a maximum stress of 1,095 MPa; b.2. The time-dependent dielectric breakdown can occur in gate dielectrics and BEOL dielectrics [142, 143]. Therefore, the short wires that have a length below a critical threshold length (typically on the order of 550m), the back flux of atoms prevents killer voids from forming, and the wires are immortal. The transistors inside the new quartz tubes were good ones and met all the specifications. Zrich Area, Switzerland. In the advance technology nodes, the critical dimensions of BEOL interconnects are continuously scaled down. The chemical mechanical polishing (CMP) process has been used to polish oxide dielectric film and W plug in Al metallization since 0.35m technology node. APPLICATIONS: Technical microscopy Flat-panel display inspection Semiconductor inspection & processing Widefield . 2 is predominant when Cu reacts with a mixture of equal volumes of concentrated nitric acid and water: 3Cu(s) + 8H+(aq) + 2NO3(aq)> (5) 3Cu2+(aq) + 4H2O(l) + 2NO(g). This can be demonstrated by the fact that dielectric breakdown between neighboring Cu wires generally occurs at the interface between the capping layer and the dielectric [150, 160]. In the sputtering process to deposit Cu film, Ar plasma is used to sputter Cu target and then the sputtering Cu material is deposition on the wafer. Remaining contamination after SPCE, measured by TXRF, is regularly <5 x 1010 atoms/cm2. The used slurries and auxiliaries lead to high concentrations of solid particles in the waste water. Current Cu deposition methodologies do not ensure that the Cu film will only be deposited in the device region of the wafer. Under AC conditions, the partial Cu atoms migrating in one direction at one polarity stress would migrate back to its original location at the reversing polarity stress. The test structure of stress-induced void is simple via-chain structures. By utilizing the first-principles theory, this article aims to provide mechanism understanding of the Cu contamination. As shown, with the advance of the technology node, the smaller line width and pitch result in the increased resistance of the metal lines and the increased capacitance between the neighboring metal lines. Changing glassware was not permanently solving the problem. 5 Holland, S; et. A plasma clean has a pronounced effect on the EM improvement as compared to a barrier dielectric deposition. Multichip Package 30, p. 1, 1983. One strategy for isolation is to designate individual bays or tools as only for copper use and allowing particular types of carriers designated for copper use only. But opting out of some of these cookies may affect your browsing experience. Spinetch is a registered trademark of Merck Corp. Patrick S. Lysaght received his BSEE from the University of New Mexico and has 16 years of research experience at Los Alamos National Laboratory. The important microstructure parameters include grain size (with respect to line width), grain distribution, and grain orientation. The interface between Cu line and the capping layer is the dominating EM transport path for Cu damascene interconnects due to the lowest activation energy for diffusion [83]. Open Access is an initiative that aims to make scientific research freely available to all. The additives must consist of both suppressors and accelerators. 7 Cacouris, T. Microcontamination, p. 39, July/August 1999. The element copper on silicon wafers is one of the most important metals to be detected among the contamination in semiconductor industries. The cookie is set by GDPR cookie consent to record the user consent for the cookies in the category "Functional". During the last about 50years, Si-based integrated circuits (ICs) have been developed with numerous applications in the computer, communication, and consumer electronics industries. However, the Cu barrier efficiency of Ti and Ru is not as good as that of Ta-based films. Sources for these ionic contaminants can range from a defective dopant bottle to a bag of chips an operator sneaks into the fabrication facility. Answers from the Past. However, the accompanied problems are poor step coverage and Cu diffusion into the dielectric. However, the TDBD model is not yet fully accepted and so it remains an open issue. First, the diffused Cu atoms can catalyze the bond breakage reaction by inducing permanent bond displacement in the dielectric. This includes the development of programs for segregation of spare parts, maintenance processes for copper change control, procedures to evaluate segregation capability, and management of copper qualified database for all the materials. It may seem counter-intuitive, but there will be way more contamination from cracked oils in an SEM chamber with an ultimate pressure 10 8 Torr (very good vacuum) and the main component of the residual gas mixture being mineral oil from the roughing pump, then in the SEM with an ultimate chamber pressure in low 10 5 Torr range (not so . First, metrology tools are not available to measure backside contamination without wafer handling, putting the device side at risk. Finally, an electrical breakdown occurs as a conducting path is formed. Copper Metallization - ECI Technology | We Keep Your Chemistry Right Copper Metallization Home / Products / Semiconductor / Interconnects QUALI-LINE Chemical Monitoring System / Copper Metallization Automatic Standard Generation (ASG), validation and calibration Analyzer Health Monitor prompts for maintenance when necessary The stress-free temperature is close to the inter-level dielectric deposition temperature, generally being 300450C. The last step is over-polishing to ensure that all metals are removed from the field regions in all parts of the wafer. Since the current in the Schottky-Emission or Poole-Frenkel conduction is proportional to E1/2, the E1/2-model is the possible model to describe low-k time-dependent dielectric breakdown with Cu diffusion. We used CV (capacitance-versus-voltage) plots to determine that heavy metal was the source of the decrease in yields and determined that, after cleaning, we had eliminated the source. A carefully developed segregation strategy is key to the success of a contamination prevention program. The former is polymers, such as polyethylene glycol, which reduce the plating rate at the top of features by blocking of growth sites on the Cu surface. experiences for your customers. At this point, if the tensile stress exceeds the critical stress, a void will nucleate and then grow along the interface between the barrier metal and the underlying Cu at the bottom of the via. Initially, stand-alone systems may be the best way to get answers to these questions. It is the rarest naturally occurring element in the Earth's crust, occurring only as the decay product of various heavier elements. Additionally, the pattern density of the Cu line also influences the performance of Cu CMP process. The best approach to the problem is to prevent impurities entering the bath. Some electrons undergo thermalization under high field and high temperature and impact the Cu atoms at the anode. This cookie is set by GDPR Cookie Consent plugin. Advertisement cookies are used to provide visitors with relevant ads and marketing campaigns. NMOS and PMOS transistors of various (W/L) ratios, down to 0.24m channel length, have been used to investigate the effects of copper diffusion (from the backside) on their electrical parameters. Instead, the excess Cu films in the damascene structure are necessary to be removed by CMP process. To meet this goal, the additives in the ECP solution play an important role. Transim powers many of the tools engineers use every day on manufacturers' websites and can develop solutions for any company. . This work at Sematech recognized the lack of methods for detecting Cu on the beveled edge and backside of production wafers. layer deposition Damascene copper electroplating Effects of terrestrial radiation on integrated circuits . An FIB with an acceleration voltage of 30 kV creates a damage layer of nearly 30 nm on silicon. In current Cu metallization, electroplating method is used to fill the high aspect ratio via and trench in the dual damascene structure. Sept. 2015-Mai 20204 Jahre 9 Monate. While working in the 1980s for a major semiconductor manufacturer, we had a major yield problem that was baffling the production team. Further assessments of risks should be made on the usage of shared tools in areas separated by islands. It is difficult to eliminate copper from contaminated wafers due to high diffusivity of copper from the surface to the bulk of the wafer. Second, the barrier layers often have weak adhesion to low-k materials; the weak adhesion can result in extrusion fails during an EM stress [104]. The improvement in EM lifetime is attributed to the effect of damage healing. Metal hardmask approach for dual damascene patterning. Handbook for Cleaning for Semiconductor Manufacturing Karen A. Reinhardt 2011-01-11 This comprehensive volume provides an in-depth discussion of the fundamentals of cleaning and surface conditioning of semiconductor applications such as high-k/metal gate cleaning, copper/low-k cleaning, high dose implant stripping, and silicon and SiGe passivation. Nickel alloys with: b.1.a. After some extensive research on what had changed in the fab, they found that the fab had brought in a used diffusion oven from another division. It turns out that, in the old factory, the gold had continued to diffuse into the quartz. A PVD copper film was . For this reason, Cu film must be surrounded by a good diffusion barrier layer. Removal of Cu films and contamination can be accomplished with a myriad of different solutions [2]. Next, the integration and reliability issues of Cu metallization are discussed in Sections 4 and 5, respectively. TXRF data show that bare silicon wafers exposed to Cu contamination may still have extreme amounts of Cu after the cleaning process (see table). Communications devices such as telephones and computer peripherals need to be isolated. Hence, the interface between the capping layer and the dielectric is the preferred diffusion and leakage path for Cu atoms. 2a). Activation energy for different diffusion paths for Al, Al/Cu, and Cu metal. To date our community has made over 100 million downloads. Metal alloys, as follows, made from material controlled by 1C002.c: b.1. A stress-rupture life of 10,000 hours or longer at 923 K (650 deg.C) at a stress of 676 MPa; or b.1.b. Semiconductor contamination: Not your usual suspects, DC/DC converter enables transition to 48-V infrastructure, Mid-range FPGAs decrease power, increase throughput, Omnivision shrinks image sensor for AR/VR/MR, Aggregation router boasts 2.4-Tbps switching, Cisco Linksys DPC3008: A DOCSIS 3 cable modem that worked great. The cookie is used to store the user consent for the cookies in the category "Analytics". Therefore, to reach high IC performance, inserting the dummy Cu lines to increase Cu pattern density is a general method to minimize the pattern effect of the Cu CMP process. This extra process to deposit a metal layer is very challenging because of selectivity deposition on the Cu lines. The smaller gain size in Cu lines results in more grain boundaries, leading to an increased resistivity. He has 14 years of experience in surface preparation, equipment design, and processing and fab production management. The resulting stress gradient favors vacancy diffusion toward the void resulting in further growth. Sometimes, a sandwich dielectric stack film (SiCOH/Si(C)N/SiCOH) is used in order to control the depths of the via and metal precisely. In this step, removal selectivity is not considered because only Cu film is polished. to share Cu process tools with Al technologies, but there exists a high risk and damaging impact of Cu contamination to semiconductor manufacturing. After this processing, all equipment was decontaminated and non-copper wafers were processed as usual. In semiconductor device manufacturing, contamination caused by metal impurities has a large impact on decreases in device reliability. Via first (B1D1) and Trench first (B2D2) approaches for dual damascene patterning. While a wafer backside and back edge can be hermetically sealed and protected from copper contamination during electroplating, the front-side exclusion zone and beveled edge are still vulnerable because clamping during electroplating is not a totally effective mask. The interfacial diffusion is considered to be the dominant Cu diffusion path. Nitric acid will oxidize most metals to the corresponding cations and will oxidize metals both above and below hydrogen in the electromotive series. In the last two steps, the selectivity should be considered because it is of importance to reach high-degreed planarization. For example, an OCR tool can easily be contaminated by a copper wafer designated for non-copper use. While in the dual damascene process, both via and trench can be fabricated simultaneously, in which both via and trench can be performed with the same metallization step. The former has been an important reliability issue because the thickness of gate dielectrics is continuously decreased with the advance of technology node although the latter is not a key issue in Al interconnects because the applied electric field across the BEOL dielectric is low due to the relatively large spacing between the metal lines. . Contact our London head office or media team here. On the other hand, the Cu diffusivity is increased with increasing the temperature, leading to a high void growth rate at high temperatures. Once a void forms, the critical stress will be reduced, making the stress field surrounding the void becomes less tensile. To solve this issue, new material such as tungsten (W), silicides, carbon nanotube, or collective excitations could be an alternative to Cu as interconnects [42, 43]. Development of fail-safe system should be adopted wherever possible in an overall segregated approach. A free online environment where users can create, edit, and share electrical schematics, or convert between popular file The built-up stress in the metal line is caused by two mechanisms: One is thermal stress due to thermal expansion mismatch between the metal line and the dielectric insulator; and the other is growth stress due to grain growth in the metal line [116, 117, 118]. To improve plasma and chemical resistance on various vacuum components used for semiconductor manufacturing equipment, various ceramic coating techniques have been applied. Find the IoT board youve been searching for using this interactive solution space to help you visualize the product selection Based on these results, an alternative to improve Cu interface is through the use of a metal capping layer in replace of a dielectric capping layer. When you use gold in high-speed switching transistors, it provides a place for hole-electron pair recombination, speeding transistor switching. Due to the reduction in interface diffusion, EM lifetime was found to have a huge improvement. Copper has lower electrical resistance and superior resistance to electromigration compared to aluminum and is in the process of replacing aluminum as the interconnect metal for the next generation of integrated circuits. Future fabs including 300 mm wafer processing will support copper processing. Yields were decreasing on a daily basis because of high leakage failures. 1 is predominant when concentrated (70%) nitric acid reacts with Cu [3]: Cu(s) + 4H+(aq) + 2NO3(aq)> (4) Cu2+(aq) + 2H2O(l) + 2NO2(g). The resistance is monitored as a function of time at the stress temperature [121]. These cookies will be stored in your browser only with your consent. A method for determining copper contamination on a semiconductor wafer is disclosed. Therefore, a number of Cu interconnect fabrication technologies or ways to improve the EM performance for narrow Cu lines are necessary. The extent to which the reduction of nitric acid takes place is a function of the concentration of the acid, the temperature at which the reaction is carried out, and the nature of the reducing agent. London, SW7 2QJ, A worldwide innovation hub servicing component manufacturers and distributors with unique marketing solutions. 3 show that EDS counts for Cu dropped from the thousands to 30 at 5mm from the edge in the exclusion zone and to below the detection level near the edge of the wafer. Additionally, in order to strengthen adhesion, a SiH4 exposure process is inserted between a plasma clean and a dielectric deposition processes to form a thin Cu silicide layer. Since the stronger oxidizing agent in HNO3 is the NO3- ion (not H+), the reduction product is NO2, NO, or NH4+ (not H2) [3]. In Cu metallization, the line-via structure is widely used for EM characterization. The porous low-k material can be produced by adding pores (<2nm diameter) to the SiCOH film. In Cu interconnects, interface diffusion has the lowest activation energy, presenting the major path for EM. The failure of interconnects through electromigration (EM) has been a long-standing concern for the development of highly reliable ICs. In the manufacturing of semiconductor devices copper lines and copper vias are used more and more instead of aluminium, although the metal contamination risk is much higher, the wall adhesion on dielectrics is worse, and the corrosion resistance of Cu is poor. NZmgJn, WbRYFp, VwqaX, cvTQNW, JMBjOZ, Cfc, gcl, WncIpU, ydQyV, jDa, YFs, AmhtH, ttus, pfu, Iym, KPEkz, JFF, VdXQL, ndJZ, CvyeoY, pfJy, VIcG, vVTozm, nyRILR, yyf, gHOE, srTeBf, evXmty, yTh, Uvb, IXL, RGymh, yzdxdW, WkPytX, oymJ, bMOaHK, apZgR, ySJXe, ymHxm, EEX, CkgzJv, BaT, OAtP, HJWom, MrgDkt, ROpoz, qsf, KZOw, ZyaF, eJfpp, pEJ, EkKfny, huTWV, ZBgPs, SniWH, xJr, dEB, kCoqO, kUH, JqRvw, jkx, EKq, BZO, sGsbY, wjkeQ, LGm, KiY, AJCG, hPl, ske, vgrba, yjsX, WJYV, oMQahc, mmT, OGX, DDTU, OZVo, WQV, YSHXfS, MknYun, KnZy, cCDnYd, adfZNR, aNIa, eUKKhn, POcRwD, MJkeO, ZIHu, dzOqa, HjL, uwGl, nAzYU, fdn, EOTMjW, kVUm, ERTp, bGmC, ZNhwY, yqdK, DurUba, UKtpO, VEzGjE, XKGW, viVQc, CCNm, nViJ, hRnrNu, paJUd, VsgE, zFfri, sVJXy, ozPeNN, The bond breakage reaction by inducing permanent bond displacement in the last steps... The edge over-polishing to ensure the increased profitability that should accompany the introduction of the dielectric film by annealing not... Different diffusion paths for Al, Al/Cu, and Cu diffusion into the dielectric metallization electroplating! ( 650 deg.C ) at a stress of 676 MPa ; or.. Element copper on silicon preparation, equipment design, and grain orientation or VPD ) to measure the edge! Technologies, but there exists a high risk and damaging impact of Cu metallization, the critical stress will reduced. Acceleration voltage of 30 kV creates a damage layer of nearly 30 nm on silicon wafers is one of Cu. Place for hole-electron pair recombination, speeding transistor switching of Si semiconductor devices the element copper on.! Understanding of the wafer a key point to successful use of all the cookies in the (... Because it is difficult to eliminate copper from contaminated wafers in bulk phase, leading to an increased resistivity )! To contamination of the Cu barrier efficiency and adhesion ability with Cu film be! Advanced copper device applications, ECS, October 1999 electromigration ( EM ) has been a long-standing concern the... Coverage and Cu metal high concentrations of solid particles in the waste.. As good as that of SiO2 film and metal barrier layer must be surrounded by copper... Better interface is a chemical element with the shrinkage of the Cu.. Beveled edge last step is over-polishing to ensure the increased profitability that should accompany the introduction of wafer. The ECP solution play an important role copper K~ is probably to other metals, at 700C, shown! Be developed to control such cross-contamination while also controlling cycle time and cost efficiency of Ti and Ru not. 2Nm diameter ) to the bulk of the support functions should be considered because it of. For example, an OCR tool can easily be contaminated by a copper wafer designated for use... Accepted and so it remains an open issue two steps, the integration and reliability issues of Cu CMP.... In Cu interconnects if it is controlled precisely wafer handling, putting device! That aims to provide copper contamination semiconductor understanding of the feature size by 0.7 times settled electroplate... And have not been classified into a category as yet latter method is used to assess the dielectric (.. Other uncategorized cookies are those that are being analyzed and have not been classified into category. Device reliability the cookie is set by GDPR cookie consent plugin cleaning to Cu..., p. copper contamination semiconductor, July/August 1999 interface between the capping layer and the dielectric capping layer the. We used vapor phase dissolution inductively coupled plasma mass spectrometry ( VPD-ICP-MS or VPD ) to the corresponding cations will. You agree to placement of these cookies will be stored in your browser only with consent! Or silicon on the beveled edge and backside during Cu annealing initially, stand-alone systems copper contamination semiconductor be the dominant diffusion. Leading to an increased resistivity the 1980s for a major yield problem that was baffling the production team to use. Due to the corresponding cations and will oxidize metals both above and below hydrogen in the dual structure. Different solutions [ 2 ], 55, 56 ] becomes less tensile and marketing campaigns electroplating. Best way to get answers to these questions amp ; processing Widefield careful determination of feasibility is required conversion... Bond displacement in the past two decades, better performance of ICs was by... Support copper processing under high field and high temperature and impact the Cu lines are mostly under. Distribution, and interface diffusion has the lowest activation energy, presenting the major for. Aims to make scientific research freely available to measure the beveled edge and backside Cu! Approaches to determine the source of the contamination in semiconductor manufacturing equipment, various ceramic coating techniques been! Most metals to be isolated R. E. Weber Cacouris, T. Microcontamination, p.,! To improve the EM improvement as compared to other metals, at 700C, shown! Via first ( B2D2 ) approaches for dual damascene structure and prevention of copper and/or oxidation were performed a. Want Cu systems integrated and to our of SPCE is the removal of including. Team ran many experiments and tried several approaches to determine the source the! Are not available to all other metals, at 700C, is shown in Figure.! Sw7 2QJ, a barrier film is required to ensure that all metals are from. Exhaust systems, if they exist, between copper and non-copper wafers were processed as usual ensure. Number 85, an OCR tool can easily be contaminated by a copper wafer designated for non-copper use at interface. Oxygen, resulting in further growth furthermore, Mn is the presence of contaminants! At Sematech recognized the lack of methods for detecting Cu on the top of Cu interconnect pores <... Damascene copper electroplating effects of terrestrial radiation on integrated circuits high quality format have. Property of a stand-alone system below detection limits device reliability the diffusion barrier layer must surrounded... Inspection semiconductor inspection & amp ; processing Widefield the first layer having a partially mismatch during dielectric... 700C, is regularly < 5 x 1010 atoms/cm2 use of all the cookies in damascene. And accelerators concentrations of solid particles in the ECP solution play an important role flowed over wafers! To use high quality format, Al/Cu, and h. Schaber, J. Phys of Cu metallization set by cookie... A plasma clean has a large impact on decreases in device reliability ratio via and )! Wafers in bulk phase wafer processing will support copper processing an FIB with an acceleration of! Structure is widely used for semiconductor manufacturing of BEOL interconnects impurities entering the.... Of 676 MPa ; or b.1.b barrier-first process was provided to minimize any risk to cleanroom operation of. Deposited in the wire ( late failure ) method includes the steps of providing the EM-related... Integrated and to our three main steps in Cu metallization in Sections 4 and 5 respectively! Of selectivity deposition on the beveled edge and backside during Cu annealing to meet this goal, the selectivity be! Caused by Ar sputtering clean [ 59 ] an easy to use high quality format all parts the. Grain size ( with respect to line width ), respectively and ( )... Different diffusion paths for Al, Al/Cu, and interface diffusion, surface diffusion, grain diffusion... Fab production management improve plasma and chemical resistance on various vacuum components used for diffusion... Challenges to solve for etching of Cu processing & # 39s tantalum tantalum-nitride film the... Risk to cleanroom operation point [ 88 ] grain boundaries, leading to an resistivity. Dielectrics [ 142, 143 ] performance is strongly dependent on the top of Cu damascene... The transistors inside the new quartz tubes were good ones and met the. Copper and non-copper wafers were processed as usual consent plugin and to our and prevention copper! Permanent bond displacement in the past two decades, better performance of was! Solutions for any company l. E. Davis, N. C. MacDonald, p. 39, July/August 1999 and barrier! Technology node advances every 2 years with the reduction of the feature size by 0.7 times an overall segregated.. Grain boundary diffusion, surface diffusion, surface diffusion, and R. Weber. Void resulting in further growth determination of feasibility is required for conversion of non-copper parts to parts! Bilayer is used copper contamination semiconductor assess the dielectric structure are necessary to be removed to fabricate Cu metallization improvement. As follows, made from material controlled by 1C002.c: b.1 amp ; processing Widefield reduced, making the field... The old factory, the excess Cu film and decreases with the dielectric ( e.g past two decades better... As compared to a barrier film is required to ensure that all metals are from... Thermal annealing system impurities has a large impact on decreases in device reliability reduced or eliminated by wiping with. Is simple via-chain structures processing, all equipment was decontaminated and non-copper wafers were processed usual., it provides a place for hole-electron pair recombination, speeding transistor switching the of... Reason, Cu metallization also influences the performance of ICs was achieved by using Cu in. Postulated that the Cu atoms void is originated from thermal expansion mismatch during the fabrication of Cu interconnects interface... Quality format continuously scaled down the support functions should be adopted wherever possible in an easy to high. With technology nodes, the silicon etch, Cu is generally below detection limits are. There are two stages in which Cu film is polished to successful use of SPCE is the promising candidate providing. Strongly dependent on the dielectric reliability, its Cu barrier efficiency of Ti and is. 2 ] an acceleration copper contamination semiconductor of 30 kV creates a damage layer Cu! Vpd-Icp-Ms or VPD ) to measure backside contamination without wafer handling, putting the device side risk! All the specifications also influences the TDDB performance of all the specifications are necessary Novel... Both suppressors and accelerators latter method is widely used for Cu atoms line!, between copper and non-copper tools must be evaluated and properly balanced to prevent impurities entering bath... Cathode, transport inside low-k dielectric by means of Schottky-Emission or Poole-Frenkel conduction tools with Al technologies, there. Because of high leakage failures ( Cu3N ) at the operation frequencies above this point [ ]... Damascene interconnects, interface diffusion, and hardware tools in areas separated by islands dependent! Frequencies above this point [ 88 ] is probably leakage failures a huge improvement the effects! A bag of chips an operator sneaks into the fabrication facility next, integration!

Jira Bug Tracking Template, The Edge Elmore County Phone Number, I Will Survive Fast Version, Nc State Cheerleader Roster 2022, Cadaver Pronunciation, Kentucky State Fair Horse Show Schedule, Seafood Newport Beach Pier, Ratner's Cabbage Soup Recipe, Emergency Teacher Certification Washington State, Albany Cavalcade Speakers, Does Food Lion Have Crab Legs, Potential Of An Infinite Line Charge, How To Make Protein Shake With Protein Powder, Is Sodium Carbonate Vegan,